Tree-Structure Architecture and VLSI Implementation for Vector Quantization Algorithms
نویسندگان
چکیده
A tree-structure based architecture for vector quantization (VQ) is proposed and implemented by VLSI in this paper. The proposed folded-tree architecture is designed by 0.8 m CMOS VLSI technology. The die size is 4.65 5.21 mm 2 and estimated clock rate is about 34MHz, which satis es most real-time applications. Since it is basically a mean squared error computation circuit, various kinds of VQ algorithms can apply on the proposed architecture.
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